The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor includes a gate electrode as a control electrode overlying a semiconductor substrate and spaced-apart source and drain regions in the substrate between which a current can flow. A gate insulator is disposed between the gate electrode and the semiconductor substrate to electrically isolate the gate electrode from the substrate. A control voltage applied to the gate electrode controls the flow of current through a channel in the substrate underlying the gate electrode between the source and drain regions.
The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs), and the IC is then referred to as a complementary MOS or CMOS circuit. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. Replacement metal gate (RMG) techniques are often employed to form the PFETs and NFETs, with gate electrode structures for the PFETs and NFETs being formed after formation of the source and drain regions. During RMG techniques, a dummy gate structure is formed that includes a gate dielectric layer, a dummy gate layer overlying the gate dielectric layer, and a nitride dummy gate cap overlying the dummy gate layer to protect the dummy gate from silicidation during source and drain formation (silicidation of the dummy gate layer would otherwise render etching of the dummy gate layer difficult). Sidewall spacers are formed adjacent to sides of the dummy gate and nitride cap, followed by source and drain region formation and deposition of a dielectric layer overlying the semiconductor substrate. The nitride dummy gate cap is removed through chemical mechanical planarization (CMP) and the dummy gate layer is then etched using appropriate etchants, leaving the sidewall spacers with a gate recess defined therebetween. Gate material is then deposited in the gate recess to form the gate electrode structures.
During fabrication of ICs with both PFETs and NFETs, different implantation and gate formation techniques are employed, resulting in variations in height of the nitride dummy gate cap for PFETs and NFETs. The variations in height of the nitride cap often impact CMP and may result in incomplete removal of the nitride cap. Without complete removal of the nitride cap, incomplete etching of the dummy gate layer may result and thereby impact device yield. Layout details including element density also impact CMP removal rates and may result in different dummy gate layer heights depending upon widths of different gates disposed on the semiconductor substrate. With different dummy gate layer heights, heights of resulting gate electrodes formed in the gate recesses result, thereby impacting quality of the ICs.
Accordingly, it is desirable to provide integrated circuits and methods of forming the integrated circuits with effective dummy gate cap removal. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.